The disclosure relates generally to methods and apparatus for controlling power consumption of a computing unit.
Computing units such as servers, smart phones, tablets, game consoles, set top boxes, laptops, wearables, printers or other devices, includes, for example, system memory and one or more processors for processing data. As shown for example in FIG. 1, a computing unit 100 includes system memory 102 (e.g., flash memory, RAM, NVRAM or other suitable memory), a processor 104 (e.g., multicore CPU) that accesses system memory 102 through a bus control hub 106 as well as a discrete graphics processing unit (GPU) 107 that includes its own discrete frame buffer memory 108 (e.g., DDRAM, NVRAM or other suitable memory). The discrete frame buffer 108 is dedicated to the discrete GPU 107 in the sense that only the discrete GPU 107 has access to store and retrieve data with the discrete frame buffer 108. In some systems, an integrated graphics processing unit 110 is integrated with the processor 104 on a same mother board or in this example, on a same chip such as an accelerated processing unit (APU) chip as the processor 104. Integrated GPU 110 uses the system memory as its frame buffer such that the system memory 102 is shared by the integrated GPU and the processor 104. The system memory 102 is coupled to the processor 104 through one or more buses 114 through the bus control hub 106. The discrete graphics processing unit 107 can be on a separate chip or circuit board and communicates with the processor 104 through a suitable bus structure shown as 116.
In this example, the integrated graphics processing unit 110 provides frames of pixels for output to display 120 and/or 122 and the discrete GPU 107 provides frames of pixels for output to display 122 and/or 120. Systems operate to reduce power consumption where possible to help mobile devices and non-mobile devices save power. In conventional systems, the discrete graphics processing unit 107 and the corresponding discrete frame buffer 108 are turned on and off together through power control logic 121 to save power, for example, when an operating system 122, driver 126 or other mechanism determines that the system or portions thereof can enter a lower power state. As shown, the processor 104 executes operating system (OS) code, other software such as application code and driver code where the driver code when executed, serves as the driver 126 to interface with the integrated GPU 110 and the discrete GPU 107. The code is stored in memory 119 and executable by the processor 104 as known in the art. The memory 119 which can be, for example, ROM, hard drive, NVRAM or any other suitable memory, stores the requisite code that when executed by the processor 104 (and/or integrated GPU 110 or discrete GPU 107), operates as the operating system, driver, power control logic, application and other suitable code as desired.
The power control logic 121 provides power control information and controls power consumption of hardware components and portions thereof through power gating logic as known in the art. The power control logic 121, as known in the art includes the requisite logic to facilitate the reduction of voltage levels and/or clock frequencies to functional blocks of CPU and GPU cores to reduce power consumption and to increase power consumption when higher performance is required. In an example, the power states are compliant with various industry standards or any other suitable power savings scheme. The power control logic 121 although shown as a block inside the processor 104, can be spread across multiple components and includes the power gating logic in the CPU, GPU and memories as well as portions of the OS and driver. In one example, the operating system 122 controls power states of the CPU and informs the driver 126 to also control power states for the integrated GPU 110 and discrete GPU 107. The integrated GPU 110 and discrete GPU 107 can also provide power control on their own by detecting non-use of functional blocks without the use of the operating system. In one example, the driver notifies the OS of the intent to shut down power. The OS evicts data in memory from portions to be shut down to frame buffer memory banks that are to be left on and the driver is notified when eviction is complete. Typically during runtime of the discrete GPU 107, the discrete frame buffer 108 is also in an on-state.
The operating system 122 typically expects a discrete GPU 107 to have its discrete frame buffer 108 on at all times during discrete GPU runtime unless both the discrete GPU 107 and the discrete frame buffer 108 are shut off together for power savings. Stated another way, a discrete GPU and its corresponding discrete frame buffer are always operated in a same state. For example, when the discrete GPU 107 is in an off-state, then the discrete frame buffer 108 is in an off-state and when the discrete GPU 107 is in an on-state, then the discrete frame buffer 108 is in an on-state. This can result in unnecessary power usage.